1. Technical Field
The present invention relates to an information processing apparatus that includes shared memory and a plurality of processors having a cache and performs directory-based coherence control and an order guarantee method which guarantee the consistency of data stored in the shared memory and the cache, and, particularly, to an information processing apparatus and an order guarantee method in which the shared memory is composed of a plurality of banks and which employs the release consistency model.
2. Background Art
In a system where a plurality of processors having a cache share memory (shared memory), when data is written to the shared memory, coherence control is necessary that invalidates data stored in the cache in each processor and thereby guarantees the consistency of data stored in the shared memory and the cache. In order to implement the coherence control, an invalidation request for invalidating (clearing) data stored in the cache is issued when a store instruction is issued by the processor. Further, in order to guarantee the completion of processing of the invalidation request, a Release instruction and a Fence instruction are used, for example.
Specifically, assuming the use of a Release processor that writes data to the shared memory and an Acquire processor that is requested to invalidate the cache data, the following control is required. The Release processor issues a Release instruction for synchronization with the Acquire processor. The Acquire processor detects the Release instruction and thereby establishes synchronization with the Release processor. The synchronism between the Release processor and the Acquire processor is the state where a result that the Release processor has accessed the shared memory is reflected on the shared memory and an invalidation request of the cache in the Acquire processor is issued in response to writing (store instruction) to the shared memory, before the issue of the Release instruction. In this stage, however, the completion of processing of the issued invalidation request is not guaranteed.
For example, Japanese Unexamined Patent Application Publication No. 2002-7371 discloses a technique of implementing the coherence control in a multiprocessor-type information processing apparatus in which a plurality of processors and a plurality of main storages are connected by a switch-type main storage control unit.
Further, in the release consistency model, the order of cache invalidation processing is not particularly fixed during a period of normal processing, which is a period until timing to guarantee the consistency of data stored in the shared memory and the cache is specified. Because the timing when the invalidation request is issued from each bank is different in the shared memory that is composed of a plurality of banks, it has been difficult to guarantee the completion of processing of the invalidation requests in each processor. Japanese Unexamined Patent Application Publication No. 2002-7371 discloses nothing about such a technique.
However, in an information processing apparatus (computer system) that shares memory composed of a plurality of banks among a plurality of processors and performs the directory-based coherence control, it is necessary to detect the timing when the consistency of data stored in the shared memory and the cache is guaranteed. Particularly, in order for the information processing apparatus to conform to the release consistency model, it is necessary to have a mechanism for guaranteeing the completion of processing of the invalidation request of the cache in each processor when the timing to guarantee the completion of processing of the invalidation request that enables the consistency of data stored in the shared memory and the cache.